Stress-impaired signal correction circuit

ABSTRACT

In a system and method for correcting a stress-impaired signal in a circuit, a calibration circuit produces a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a voltage proportional to absolute temperature. A set of reference values are generated based on these voltages. A gain correction factor is calculated based on a function of the set of reference values and a set of temperature-dependent values, and the stress-impaired signal is corrected based on the gain correction factor.

BACKGROUND

Bandgap reference circuits are used in systems That require a reference voltage that is relatively accurate and stable. A bandgap reference circuit generally includes two p-n junctions operating at different current densities. The circuit may produce a reference voltage calculated by summing a voltage across one of the junctions with a scaled difference of the voltages across both junctions. Since each junction voltage is inversely proportional to temperature and the scaled difference is directly proportional to temperature, the sum is temperature independent. In a conventional Brokaw bandgap reference circuit, the foregoing voltages are achieved by forcing a current through two bipolar transistors with different emitter areas.

Even though bandgap reference circuits are generally considered to be accurate, mechanical and/or environmental stresses (e.g., caused by circuit packaging and mounting, temperature variations, oxidation, etc.) may cause non-uniformities and voltage instability over time. Accordingly, circuit designers have sought to compensate for such stress-induced inaccuracies.

To reduce sensitivity to package stress, most high-performance voltage references are packaged in expensive open cavity hermetic packages such as ceramic or metal can. Other solutions include implementing a stress gauge using a MOS (metal-oxide-semiconductor) device, or suspending a voltage reference core on a micro-machined membrane. These mechanisms have not produced a consistent stress response, and generally cannot compensate for unstable input signals.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are presented to aid in the description of example aspects and are provided solely for illustration of the embodiments and not limitation thereof.

FIG. 1 is a chart depicting exemplary stress sensitivity of vertical pnp and npn devices, according to various aspects of the present disclosure.

FIG. 2 is a diagram of an example system that corrects errors introduced by stresses on components of the system, according to various aspects of the present disclosure.

FIGS. 3A and 3B are diagrams of further example systems that correct errors introduced by environmental and mechanical stresses, according to various aspects of the present disclosure.

FIG. 4 is a diagram of an example system that corrects an output voltage of a regulator due to stress-impaired signals introduced into a regulator, according to various aspects of the present disclosure.

FIG. 5 depicts an example circuit for generating stress-compensated bandgap voltage references, according to various aspects of the present disclosure.

FIG. 6 is a flowchart of an exemplary process for correcting a stress-impaired signal within a circuit, according to various aspects of the present disclosure.

DETAILED DESCRIPTION

In some circuit applications, certain generated signals may be based on a voltage reference that is subject to stresses, and which cannot be verified as accurate or stable. For example, a circuit may be designed to utilize an external voltage reference that is unknown at the time of design. Another circuit may produce observable signals that, over time, become degraded due to stresses not present at the time of design or implementation. It is desirable to ensure the accuracy of a reference voltage used by a circuit component, or to ensure the accuracy of the output of the component that uses such a reference voltage, irrespective of how the components of the circuit were originally designed or implemented.

The system of the present disclosure provides automatic signal correction that compensates for errors introduced by stresses on the circuit providing the signal. These stresses may occur internal or external to a particular component's packaging. The system of the present disclosure may benefit applications utilizing a signal path, including systems implementing an analog-to-digital converter and/or a voltage reference. An example system is disclosed that implements a calibration circuit, a multiplexer, and a processing unit to facilitate correction of a stress-impaired output signal of an analog-to-digital converter.

In some implementations, the disclosed calibration circuit provides a first calibrated pnp voltage based on a base-emitter voltage of one or more pnp transistors and a second calibrated npn voltage based on a base-emitter voltage of one or more npn transistors. The multiplexer is connected to the calibration circuit and a sense terminal, and provides an analog signal selected from the voltages provided by the calibration circuit and a sense voltage provided by a sense terminal. The analog-to-digital converter generates a digital output signal based on the analog signal provided by the multiplexer and a stress-impaired reference voltage.

The processor is configured to (e.g., based on an instruction set) control the multiplexer to sample the first calibrated voltage, the second calibrated voltage, and the sense voltage for the analog-to-digital converter. The processor receive a set of reference values from the analog-to-digital converter based on the stress-impaired reference voltage and a sampling of the first calibrated voltage and the second calibrated voltage by the multiplexer, and calculates a gain correction factor based on a set of reference values and a set of temperature-dependent values. The disclosed system is configured to adjust the sense voltage output from the analog-to-digital converter based on the gain correction factor to correct for errors introduced by the stress-impaired reference voltage.

FIG. 1 is a chart depicting exemplary stress sensitivity of vertical pnp and npn devices, according to various aspects of the present disclosure. Mechanical stresses on a transistor device are known to directly impact the base-emitter voltage Vbe of the transistor. This phenomenon is known as the piezojunction effect, and is a known cause of inaccuracies in precision-critical devices that utilize transistors.

The piezojunction effect and its relationship between Vbe and stress are depicted in FIG. 1. There is a known relative change in the voltage potential between base and emitter Vbe for respective vertical npn and pnp devices as a function of stress. Under certain circumstances, the stress sensitivity of a pnp device under compressive stress is known to be approximately half of the stress sensitivity of an npn device.

Conventional bandgap and temperature sensing devices have sought to study the piezojunction effect relative to a piezoresistive effect, which measures a change in a resistivity of a semiconductor or metal when mechanical strain is applied. The calibration bandgap circuit disclosed herein uses the difference in stress sensitivities of both pnp and npn for compensation. Both npn and pnp devices are sub-surface devices, and the correlation between their stress response is significantly better than the correlation between a bipolar device and a MOS device (e.g., surface current, shallow trench isolation stress), or a bipolar device and a polysilicon resistor in the metal stack, away from the silicon substrate). In this regard, the disclosed calibration circuit derives an absolute change in a bandgap voltage from stress on a pnp circuit, as well as a change in a npn circuit. Outputs of both sub-circuits are then utilized, and a difference between the npn and pnp bandgap references is used in stress calibration.

FIG. 2 is a diagram of an example system 200 that corrects errors introduced by stresses on components of the system, according to various aspects of the present disclosure. Analog-to-digital converters (ADCs) are one application in which results are dependent upon the accuracy of a voltage reference. For example, ADCs often require a voltage reference input, and the accuracy of the reference may directly influence the accuracy of the converter output. In the depicted example, an ADC 202 uses a Vref 204 that cannot be verified as accurate or stable. The output of the ADC is corrected based on a combination of npn and pnp bandgap references,

System 200 includes ADC 202, a Vref 204, a multiplexer (MUX) 206, a calibration circuit 208, a processing unit 210, and a digital gain correction buffer 212 (e.g., a cache or other memory). In some aspects, one or more these components may be integrated into a single chip. For example, ADC 202, MUX 206, calibration circuit 208, processing unit 210, and buffer 212 may be integrated as a single component and/or chip. In other aspects, the components may be implemented on two or more discrete components and/or chips.

Processing unit 210 may include a multi-core processor, a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gated logic, discrete hardware components, or a combination of the foregoing. Processing unit 210 may be configured to execute code or instructions to perform the operations and functionality described herein. For example, processing unit 210 may be configured to perform calculations and generate commands. In some implementations, one or more sequences of instructions may be stored as firmware on memory within processing unit 210. In some implementations, one or more sequences of instructions may be software stored and read from a storage medium (not shown).

Processing unit 210 may monitor and control the operation of the components in system 200, including MUX 206. For example, processing unit 210 may select respective input MUX channels for input to ADC 202, sample the output of ADC 202, and perform operations on multiple outputs based on multiple input MUX selections to generate a result. The result may be stored and/or updated within buffer 212.

ADC 202 may be a conventional measurement device that converts an input analog voltage Vin (or current) to a digital representation proportional to the magnitude of the input voltage (or current). In the depicted example, the output digital signal Vout is computed based on a function of Vin and reference voltage Vref. ADC 202 may sample multiple input voltages using MUX 206.

According to various implementations, system 200 is configured to calibrate a stress-impaired output signal, such as that produced by ADC 202. As will be described further, calibration circuit 208 provides a first calibrated pnp voltage Vcal_pnp based on a base-emitter voltage of one or more pnp transistors and a second calibrated npn voltage Vcal_npn based on a base-emitter voltage of one or more npn transistors. One or more sense terminals 214 may provide one or more respective sense voltages Vsns_n. In the depicted example, multiplexer 206 is connected to the calibration circuit and one or more sense terminals 214, and configured to provide an analog signal selected from one of a sense voltage, the first calibrated pnp voltage Vcal_pnp, and the second calibrated npn voltage Vcal_npn. ADC 202 is configured in the system to generate a digital output signal based on the analog signal selected by the multiplexer and reference voltage Vref 204 (which may be a stress-impaired reference voltage).

Processing unit 210 controls the multiplexer to sample the first calibrated voltage, the second calibrated voltage, and the sense voltage Vsns_n for the analog-to-digital converter. The sampling may be performed according to a clock signal (not shown) or other timing mechanism. In this regard, ADC 202 generates a set of reference values based on the stress-impaired reference voltage and a sampling of the first calibrated pnp voltage Vcal_pnp and the second calibrated npn voltage Vcal_npn (the “calibration voltages”) by the multiplexer. Processing unit 210 receives the set of reference values from ADC 202 (e.g., via a signal bus) and calculates a gain correction factor G based on a set of reference values and a set of temperature-dependent values. As will be described further, the set of temperature-dependent values may be determined in real time based on the sampled values by ADC 202 and a predetermined algorithm, or may include predetermined values calculated based on training data.

The calculated gain correction factor G is used to adjust the digital output signal Vout, to correct for errors introduced by stress on the system (including, e.g., from the stress-impaired reference Vref 204). The gain correction factor G is calculated to bring the error in the measurement of sense voltage Vsns_n to zero. In this regard, G=Vref/Vref(ideal) and effectively self-calibrates the lower precision Vref. Accordingly, processing unit 210 operates multiplexer 206 to read and convert both the sense voltage Vsns_n it is seeking to correct as well as the real-time calibration voltages used to correct the sense voltages, with both the sense voltages and the calibration voltages potentially being impaired by the same stress factors.

To calculate the gain correction factor G, processing unit 210 may first initialize a device temperature parameter to a predetermined default temperature (e.g., T=300 K), and an initial gain correction value to a default gain correction value (e.g., G=1). The multiplexer 206 is controlled to sample the calibration voltages Vcal_pnp and Vcal_npn. In some implementations, multiplexer 206 is further controlled to sample a voltage that is proportional to absolute temperature (PTAT) Vptat. Vptat may be based on the base-emitter voltage of the one or more pnp transistors of calibration circuit 208. ADC 202 continuously samples and converts the calibrated bandgap voltages Vptat, Vcal_npn, and Vcal_pnp to corresponding reference values c0, c1, and c2.

The set of temperature-dependent values used in the previously-described calculation of gain correction factor G may be determined based on a current value of T. In some implementations, processing unit 201 may determine temperature-dependent values β0(T), β1(T), and β2(T) corresponding to reference values c0, c1, and c2 generated by ADC 202. A temperature-dependent value α(T) may also be determined. These temperature-dependent values may be determined by indexing a lookup table based on a current device temperature T, or may be calculated in real time based on sampled values. Each of these values may be initially set to a default value.

According to various implementations, device temperature T for system 200 may be calculated based on a first of the reference values c0 and the initial gain correction factor and, in some implementations, further based on the predetermined temperature-dependent value α(T). For example, processing unit 210 may calculate the device temperature according to the equation:

T=α(T)Gc0   (1)

where α(T) is a previously calculated or default T, and G is a previously-calculated or default G.

In some implementations, processing unit 210 calculates the new gain correction factor by multiplying the each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum. For example, processing unit 210 may calculate the new gain correction factor according to the equation:

G=1/(β0(T)c0+β1(T)c1+β2(T)c2)   (2)

In some implementations, the calculations of temperature T, temperature-dependent values β0(T), β1(T), β2(T), and α(T), and gain correction factor G are repeated until temperature T and gain correction factor G converge to respective values (e.g., according to a predetermined convergence algorithm). The (uncorrected) output signal Vout of ADC 202 may then be corrected by multiplying the magnitude of the output signal Vout by gain correction factor G. In some implementations, processing unit 210 may store a final value of T, and provide T as an output value. Since device temperature T by way of the calculations described herein (and/or, e.g., by way of convergence) becomes a corrected value, system 200 may function as a stress-compensated integrated temperature sensor by providing T as an output value.

In some implementations, processing unit 210 determines the gain correction factor G from one or more polynomial equations. For example, processing unit 201 may determine temperature-dependent values β0(T), β1(T), and β2(T), and α(T), in the forgoing manner. The polynomial equations may be generated based on the set of temperature-dependent values, the set of reference values c0, c1, and c2, the calibrated bandgap voltages Vptat, Vcal_npn, and Vcal_pnp, and the stress-impaired reference voltage Vref. The polynomial equations may then be solved for unknowns G and a change in stress Δσ, as described further below.

ADC 202 continuously samples and converts a set of calibration voltages selected by multiplexer 208 from calibration circuit 208 to reference values c0, c1, and c2. One or more of these calibration voltages may be a linear combination of a base-emitter voltage of the one or more transistors and a PTAT voltage. In some implementations, the linear combination may include other voltage components such as curvature-compensation voltages. According to various implementations, the set of reference values are based on at least one base-emitter voltage derived from a pnp transistor and at least one base-emitter voltage derived from an npn transistor.

FIGS. 3A and 3B are diagrams of further example systems 300 that correct errors introduced by environmental and mechanical stresses, according to various aspects of the present disclosure. In these example implementations, the set of reference values omit one of the previously-described base-emitter voltages, and instead include a combination of a reference value based on a base-emitter voltage derived from a pnp transistor and a reference value based on a pure PTAT voltage (FIG. 3A), or a combination of a reference value based on a base-emitter voltage derived from an npn transistor and a reference value based on a pure PTAT voltage (FIG. 3B).

In the depicted examples, calibration circuit 208 generates calibration bandgap voltages Vptat and Vcal_npn, or Vptat and Vcal_pnp. Reference values c0 and c1 are generated by ADC 202, and temperature-dependent values β0(T), β1(T), and α(T) are determined, as described with regard to FIG. 2. In some implementations, gain correction factor G may be calculated by solving for unknown polynomial equations based on these determined values. In some implementations, gain correction factor G may be calculated by multiplying the each temperature-dependent value (e.g., β0(T) and β1(T)) by a respective reference value (e.g., c0 and c1), summing each result, and determining a reciprocal of the sum.

With regard to FIGS. 3A and 3B, the type of calibration circuit 208 used in a system 300 may be based on the component type of ADC Vref 204. In this regard, the calibration voltage omitted from calibration circuit 208 may be complimentary to the bipolar type implemented by ADC Vref 204. For example, if Vref 204 is derived from npn devices then a calibration circuit 208 may be used that omits Vcal_npn and implements Vcal_pnp. If Vref 204 is derived from pnp devices then a calibration circuit 208 may be used that omits Vcal_pnp and uses Vcal_npn. In other words, if calibration circuit 208 omits Vcal_npn then ADC Vref 204 may be based on npn devices. If calibration circuit 208 omits Vcal_pnp then ADC Vref 204 may be based on pnp devices.

FIG. 4 is a diagram of an example system 400 that corrects an output voltage of a regulator due to stress-impaired signals introduced into a regulator, according to various aspects of the present disclosure. As described with respect to FIGS. 2 and 3, system 400 includes an ADC 202, a Vref 204, a multiplexer (MUX) 206, a calibration circuit 208, a processing unit 210, and a digital gain correction buffer 212. System 400 also includes a digital-to-analog converter (DAC) 216 and voltage regulator circuit 218.

System 400 is coupled to regulator circuit 218 to correct the output Vout of the regulator circuit. In the depicted example, multiplexer 206 is connected to calibration circuit 208 and regulator output voltage Vout as a sense terminal 214, and configured to provide an analog signal selected from one of regulator output voltage Vout, the first calibrated pnp voltage Vcal_pnp, and the second calibrated npn voltage Vcal_npn.

In the depicted example, DAC 216 receives the corrected output of ADC 202 based on a servo loop control algorithm 220. Algorithm 220 controls the sequencing, timing, and computational capabilities of a servo loop. In some implementations, servo loop control algorithm 220 is executed by processing unit 210. In some implementations the algorithm is implemented in a servo loop controller (at reference 220 in FIG. 4), positioned between ADC 202 and DAC 216 to receive the corrected output of ADC 202. The output of ADC 202 or digital servo controller 220 is converted to analog form by a DAC 216, and is further provided to regulator circuit 218 as a reference voltage. In some implementations, the precision of the digital to analog conversion is due to a relatively slow servo loop. The voltage regulator is configured, by way of the servo loop, to handle fast output transients and load/line regulation.

Those skilled in the art will appreciate that information and signals produced by or within the systems and circuits described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

FIG. 5 depicts an example circuit 500 for generating stress-compensated bandgap voltage references, according to various aspects of the present disclosure. In the depicted example, two very high-precision bandgap voltage references are created—one implemented by a first reference circuit 502 with vertical pnp transistors, and a second reference circuit 504 with a vertical npn transistor. The two device types respond to the same or similar stresses, with different sensitivity, and based on the deviation between the two trimmed bandgap references, circuit 500 may facilitate estimation and/or correction of the absolute error of an effective voltage reference due to a change in stress of the overall circuit. Circuit 500 also generates a calibrated reference voltage that is proportional-to-temperature (Vptat).

Reference circuit 502 generates a voltage reference Vcal_pnp. Reference circuit 502 includes first and second pnp transistors, Q1 and Q2, in a matched pair configuration (e.g., in a current mirror configuration or differential pair configuration). In the depicted example, reference circuit 502 implements Q1 and Q2 in a differential pair configuration. The emitter areas of each transistor may be different with, e.g., the emitter area of Q2 being N times the emitter area of Q1. In the depicted example, N=8. Transistors Q1 and Q2 are connected in parallel at their emitters to a common current source MP1. In the depicted example, MP1 is a p-channel mosfet. For the purpose of this disclosure, the acronym “MP” is used to designate a p-channel mosfet, while the acronym “MN” is used to designate an n-channel mosfet. It is understood that the types of mosfets used may be interchangeable with minor circuit variations.

According to some implementations, a dynamic element matching component DEM may be connected at the respective bases and collectors of Q1 and Q2, and is configured to employ dynamic element matching to cycle between the transistors of the matched input pair to compensate for localized stress effects. The collector currents I1 and I2 through R1, and R2 and R3, respectively may be held constant and equalized.

Resistors R4 and R5 function as a voltage divider, creating a voltage potential Vn1 at node n1 to bias Q1, and a base current IbaseQ1 sums into node n1 (between R4 and R5) from the base of Q1, creating a beta sensitivity (e.g., at the base of Q2). The R4/R5 voltage divider is powered by a current flowing through a current source MN1. MN1 is controlled by amplifier I0, and a difference between voltage potentials Vn2 and Vn3 across R1 and R2, respectively.

A voltage potential Vn4 is created based on an output of a second voltage divider, which divides voltages across resistors R6 and R7 connected to the base of Q2. When operational, MN2 draws an equal amount of current away from R5. MN2 is controlled by amplifier I1 and a difference between voltage potentials Vn1 and Vn4. According to various implementations, MN2 draws a current Imn2 that is equal to the current IbaseQ1 (through the base of Q1). By removing Imn2 from node n1—and thus R5—the voltage drop across R5 (e.g., measured at Vn4) accurately represents a proportional-to-temperature (PTAT) voltage without base current errors.

According to various implementations, the amplifier I2 controls current source MP1 based on a difference between, e.g., voltage potential Vn4 and voltage potential Vn2 (across R1). In this regard, amplifier I2 forces the collector currents of Q1 and Q2 to be PTAT, in addition to the collector currents being equal.

Second reference 504 circuit includes an amplifier I3 which controls MN3 based on, e.g., a difference between Vn4 and an a voltage divider output Vn5 based on resistors R8 and R9. When MN2 draws a current Imn2 (e.g., equal to or based on IbaseQ1), node n1 (between R4 and R5) and node n4 (between R6 and R7) are forced to the same (PTAT) potential. Vn4 may then be mirrored and gained upward by amplifier I3 and MN3 (e.g., based on the values selected for R8, R9, and R10) to generate Imn3. A PTAT voltage potential across resistors R8 and R9 is generated and output as a PTAT reference voltage Vptat.

Reference circuit 504 further generates a voltage reference Vcal_npn. Reference circuit 504 includes a current mirror in which PTAT current Imn3 is copied by amplifier I4 and MP2 as a PTAT current Imp2. Amplifier I5 is configured as a unity buffer to maintain equal emitter and collector voltages of the npn transistor Q3. The emitter area of Q3 may be different than the emitter area of Q1 and Q2, e.g., with the emitter area of Q3 being X times the emitter area of Q1. In the depicted example, X=28. PTAT current Imp2 creates a base-emitter voltage potential in Q3, which is also PTAT and output as Vcal_npn.

In addition to the global package stresses, the silica particles in the mold compound fill used in plastic packages may create point stresses on the device surface. The variation of the point stresses over time and temperature can result in significant change in the absolute voltage of the bandgap reference. In some instances, if a silica particle applies stress directly over the 1x device in a bandgap core of the device, the device can exhibit aberrant performance over temperature. To mitigate this effect, some processes offer relatively thick conformal coatings over the die surface such as polyimide or PBO. To reduce the effects of local stresses even further, some implementations of circuit 500 may alternate the position of Q1 (e.g., within the die). By using spatial averaging, the effective bandgap voltage may correspond to an average stress in the bandgap core. The npn devices Q3 may be located inside a Q1/Q2 array in a centroid fashion in order to be subjected to the same average stress as the pnp devices.

As described previously, the subject technology determines temperature-dependent values β0(T), β1(T), and β2(T) corresponding to reference values c0, c1, and c2 generated by ADC 202. These temperature-dependent values may be determined from a lookup table based on a current temperature T, or may be calculated in real time based on sampled values, and may be used in a calculation of gain correction factor G. Additionally or in the alternative, polynomial equations may be solved for unknowns G and a change in stress Δσ. These polynomial equations may also be based on a combination of the set of temperature-dependent values (e.g., β0(T), β1(T), β2(T), and α(T)), the set of reference values (e.g., c0, c1, and c2), a stress-impaired reference voltage Vref, in addition to the calibration bandgap voltages (e.g., Vptat and Vcal_npn and/or Vcal_pnp).

The following examples are provided to explain how the set of temperature-dependent values and/or the polynomial equations used to solve for G may be developed (e.g., based on real time values or on training data).

FIRST EXAMPLE IMPLEMENTATION

Using the three voltages V_(PTAT), V_(CALNPN) and V_(CALPNP) generated by the calibration circuit 208, two high-precision bandgap references can be defined (with the coefficients g₁and g₂ may be a function of the design):

$\begin{matrix} {{V_{{BG}_{NPN}} = {V_{{CAL}_{NPN}} + {g_{1}V_{PTAT}}}}{V_{{BG}_{PNP}} = {V_{{CAL}_{PNP}} + {g_{2}V_{PTAT}}}}{T = {\alpha \frac{V_{PTAT}}{V_{{REF}{({Ideal})}}}}}} & (3) \end{matrix}$

Coefficients g₁ and g₂ may be a function of the design and α is a final trim coefficient. The temperature T can be calculated from a final test trim coefficient α and an ideal reference voltage V_(REF(Ideal)). In the following derivation all parameters are a function of the device temperature T, with the exception of V_(REF(Ideal)). The synthesized voltage references V_(BG) _(NPN) and V_(BG) _(PNP) are affected by many circuit error sources, an initial package stress (e.g., represented by coefficient σ_(trim)) determined when the device was trimmed at final test, and a change in stress due to aging of the package and the additional board-mounting stress Δσ.

Using the example circuit topology of FIG. 5, and chopping and dynamic element matching, the bandgap voltages can be made insensitive to circuit imperfections. Over time, the stress transmitted to the bandgap core will change by Δσ, and the voltage references V_(BG) _(NPN) and V_(BG) _(PNP) will change according to the following equation:

V _(BG) _(NPN) =V _(BG) _(NPN) _((Trim)) +V _(REF(Ideal)) Σ_(n=1) ^(N) a _(n)(Δσ)^(n)

V _(BG) _(PNP) =V _(BG) _(PNP) _((Trim)) +V _(REF(Ideal)) Σ_(n=1) ^(N) b _(n)(Δσ)^(n)   (4)

where a_(n) and b_(n) are example stress sensitivity coefficients (which may be different), and V_(REF(Trim)) and V_(CAL(Trim)) are the respective values when the device is subject to initial package stress and trimmed according to a final test coefficient.

During normal operation, ADC 202 may measure the ratio between the three voltages V_(CAL) _(NPN) , V_(CAL) _(PNP) and V_(PTAT) produced by the calibration bandgap voltages and the ADC reference voltage 204 (V_(REF)) with very high precision, even though the absolute value of V_(REF) may have large errors:

$\begin{matrix} {{c_{0} = \frac{V_{PTAT}}{V_{REF}}}{c_{1} = \frac{V_{{CAL}_{NPN}}}{V_{REF}}}{c_{2} = \frac{V_{{CAL}_{PNP}}}{V_{REF}}}} & (5) \end{matrix}$

The ADC reference values c₀, c₁ and c₂ corresponding to the conversion of the three calibration bandgap voltages may be used to calculate the following ratios (substituting (5) in (3)):

$\begin{matrix} {{\frac{V_{{BG}_{NPN}}}{V_{REF}} = {c_{1} + {g_{1}c_{0}}}}{\frac{V_{{BG}_{PNP}}}{V_{REF}} = {c_{2} + {g_{2}c_{0}}}}} & (6) \end{matrix}$

In one example, the ADC gain correction factor G used in the digital gain correction block in FIG. 2 is determined to scale the non-ideal ADC output codec_(ADC):

$\begin{matrix} {{G = \frac{V_{REF}}{V_{{REF}{({Ideal})}}}}{c_{ideal} = {\frac{V_{ADC}}{V_{{REF}{({Ideal})}}} = {{G\left( \frac{V_{ADC}}{V_{REF}} \right)} = {Gc}_{ADC}}}}} & (7) \end{matrix}$

The initial values of the bandgap voltages at final test may be stored in memory as the ratios g₃, g₄:

$\begin{matrix} {{g_{4} = \frac{V_{{BG}_{PNP}{({Trim})}}}{V_{{REF}{({Ideal})}}}}{g_{3} = \frac{V_{{BG}_{NPN}{({Trim})}}}{V_{{REF}{({Ideal})}}}}} & (8) \end{matrix}$

Substituting (5) in (6) yields:

$\begin{matrix} {{\frac{V_{{BG}_{NPN}{({Trim})}}}{V_{REF}} = \frac{g_{3}}{G}}{\frac{V_{{BG}_{PNP}{({Trim})}}}{V_{REF}} = \frac{g_{4}}{G}}} & (9) \end{matrix}$

Dividing (4) by V_(REF) and substituting (6) and (9) yields two polynomial equations for the two unknowns G and Δσ:

$\begin{matrix} {{{c_{1} + {g_{1}c_{0}}} = {\frac{g_{3}}{G} + {\frac{1}{G}{\sum\limits_{n = 1}^{N}{a_{n}({\Delta\sigma})}^{n}}}}}{{c_{2} + {g_{2}c_{0}}} = {\frac{g_{4}}{G} + {\frac{1}{G}{\sum\limits_{n = 1}^{N}{b_{n}({\Delta\sigma})}^{n}}}}}} & (10) \end{matrix}$

In some implementations, the two equations can be solved by eliminating the gain correction factor G first and then finding the Δσ from the roots of an n-th degree polynomial:

$\begin{matrix} {{{\sum\limits_{n = 1}^{N}{\left( {\frac{a_{n}}{c_{1} + {g_{1}c_{0}}} - \frac{b_{n}}{c_{2} + {g_{2}c_{0}}}} \right)({\Delta\sigma})^{n}}} + \left( {\frac{g_{3}}{c_{1} + {g_{1}c_{0}}} - \frac{g_{4}}{c_{2} + {g_{2}c_{0}}}} \right)} = 0} & (11) \end{matrix}$

In some implementations, a first order approximation (N=1) may be used, and thus the equations may simplify to:

G(c ₁ +g ₁ c ₀)−g ₃ =a ₁Δσ

G(c ₂ +g ₂ c ₀)−g ₄ =b ₁Δσ  (12)

For example, the closed form solution for the gain correction factor G may be a simple multiply and accumulate operation (MAC) between the ADC conversion codes c₀, c₁ and c₂ and the trim coefficients β₀, β₁ and β₂, followed by an inversion:

$\begin{matrix} {\frac{1}{G} = {{\beta_{0}c_{0}} + {\beta_{1}c_{1}} + {\beta_{2}c_{2}}}} & (13) \end{matrix}$

where, in some implementations:

$\begin{matrix} {{\beta_{0} = \frac{g_{1} - {g_{2}\left( \frac{a_{1}}{b_{1}} \right)}}{g_{3} - {g_{4}\left( \frac{a_{1}}{b_{1}} \right)}}}{\beta_{1} = \frac{1}{g_{3} - {g_{4}\left( \frac{a_{1}}{b_{1}} \right)}}}{\beta_{2} = \frac{1}{g_{4} - {g_{3}\left( \frac{b_{1}}{a_{1}} \right)}}}} & (14) \end{matrix}$

All trim coefficients in the foregoing examples may be a function of the temperature T. Accordingly, an equation solver may start by estimating the temperature using the uncorrected voltage reference: T′=αV_(PTAT)/V_(REF). All trim coefficients β₀, β₁, and β₂ may be calculated as temperature-dependent values at the estimated temperature T′ and then the gain correction factor G determined. The next iteration for the temperature estimate may be T=αG V_(PTAT)/V_(REF), and the process may be performed a few times until the solutions for G and T converge.

To summarize, a first order stress-compensation algorithm implemented by the subject technology may include:

-   -   1. Initialize the temperature to T=300K (value is not critical,         should be in the normal operating conditions).     -   2. Initialize the gain correction factor to G=1.     -   3. Using the ADC, convert the calibration bandgap voltages         V_(PTAT), V_(CAL) _(NPN) and V_(CAL) _(PNP) and to get the ADC         codes c₀, c₁ and c₂.     -   4. Calculate the temperature T=α(T)Gc₀.     -   5. Using digital lookup tables, calculate the values of the         temperature-dependent trim coefficients β₀(T), β₁ (T) and β₂(T)         and α(T).     -   6. Calculate x=β₀(T)c₀+β₁(T)c₁+β₂(T)c₂.     -   7. Calculate G=1/x.     -   8. Repeat steps (4-7) until the estimates for T and G converge.

SECOND EXAMPLE IMPLEMENTATION

When the ADC reference V_(REF) (204) is based on a high-precision bandgap voltage (e.g., npn or pnp) and calibration circuit 208 is based on a complementary bipolar type, producing the voltages V_(CAL) (e.g., Vcal_pnp or Vcal_npn) and V_(PTAT), the stress compensation may require only two ADC conversions:

$\begin{matrix} {{c_{0} = \frac{V_{PTAT}}{V_{REF}}}{c_{1} = \frac{V_{CAL}}{V_{REF}}}} & (15) \end{matrix}$

The temperature T may be calculated from the final test trim coefficient α and the ideal reference voltage V_(REF(Ideal)). In the following derivation all parameters are a function of the device temperature T, with the exception of V_(REF(Ideal)).

$\begin{matrix} {T = {\alpha \frac{V_{PTAT}}{V_{{REF}{({Ideal})}}}}} & (16) \end{matrix}$

When high-precision design techniques are used, the stress-dependence of the V_(REF) and V_(CAL) voltages may include:

V _(REF) =V _(REF(Trim)) +V _(REF(Ideal)) Σ_(n=1) ^(N) a _(n)(Δσ)^(n)

V _(CAL) =V _(CAL(Trim)) +V _(REF(Ideal)) Σ_(n=1) ^(N) b _(n)(Δσ)^(n)   (17)

Where a_(n) and b_(n) are example stress sensitivity coefficients, and V_(REF(Trim)) and V_(CAL(Trim)) are the respective values when the device is subject to initial package stress and trimmed according to a final test coefficient.

Dividing the first equation in (17) by V_(REF(Ideal)) yields:

$\begin{matrix} {G = {\frac{V_{REF}}{V_{{REF}{({Ideal})}}} = {\frac{V_{{REF}{({Trim})}}}{V_{{REF}{({Ideal})}}} + {\sum\limits_{n = 1}^{N}{a_{n}({\Delta\sigma})}^{n}}}}} & (18) \end{matrix}$

Dividing the second equation in (17) by the first equation in (17) yields:

$\begin{matrix} {c_{1} = {\frac{V_{CAL}}{V_{REF}} = \frac{V_{{CAL}{({Trim})}} + {V_{{REF}{({Ideal})}}{\sum\limits_{n = 1}^{N}{b_{n}({\Delta\sigma})}^{n}}}}{V_{{REF}{({Trim})}} + {V_{{REF}{({Ideal})}}{\sum\limits_{n = 1}^{N}{a_{n}({\Delta\sigma})}^{n}}}}}} & (19) \\ {c_{1} = {\frac{V_{CAL}}{V_{REF}} = \frac{\frac{V_{{CAL}{({Trim})}}}{V_{{REF}{({Ideal})}}} + {\sum\limits_{n = 1}^{N}{b_{n}({\Delta\sigma})}^{n}}}{G}}} & (20) \end{matrix}$

The two coefficients β₀(T)=V_(REF(Trim))/V_(REF(Ideal)) and β₁(T)=V_(CAL(Trim))/V_(REF(Ideal)) may be determined at final test, and may be used to derive a polynomial system of equations for G and Δσ by substituting β₀(T) and β₁(T) in (18) and (20), respectively:

G=β ₀(T)+Σ_(n=1) ^(N) a _(n)(Δσ)^(n)

c ₁ G=β ₁(T)+Σ_(n=1) ^(N) b _(n)(Δσ)^(n)   (21)

A next iteration for a temperature estimate can be calculated after the gain correction factor G is determined from (25) and may include the equation T=α(T)Gc₀. The foregoing process may be performed until G and T converge to respective stable values (e.g., according to a predetermined convergence algorithm).

FIG. 6 is a flowchart of an exemplary process for correcting a stress-impaired signal within a circuit, according to various aspects of the present disclosure. For explanatory purposes, the various blocks of exemplary process 600 are described herein with reference to FIGS. 1-5, and the components and/or processes described herein. The one or more of the blocks of process 600 may be implemented, for example, by any of the various switched capacitor regulator circuits described herein. In some implementations, one or more of the blocks may be implemented apart from other blocks, and by one or more different processors or devices. Further for explanatory purposes, the blocks of exemplary process 600 are described as occurring in serial, or linearly. However, multiple blocks of exemplary process 600 may occur in parallel. In addition, the blocks of exemplary process 600 need not be performed in the order shown and/or one or more of the blocks of exemplary process 600 need not be performed.

In the depicted exemplary flow diagram, ADC 202 receives, from calibration circuit 208, a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors (e.g., Vcal_pnp), a second calibrated voltage based on a base-emitter voltage of one or more npn transistors (e.g., Vcal_npn), and a stress-impaired reference voltage (e.g., Vref) (602). ADC 202 may also receive a voltage that is proportional to absolute temperature (e.g., a “calibrated PTAT voltage” or Vptat) based on a base-emitter voltage of one of the pnp transistors. According to various implementations, these voltages are initially generated by calibration circuit 208, selected by multiplexer 206, and converted to a digital value by ADC 202.

According to various implementations, calibration circuit 208 may operate first and second pnp transistors in a matched pair configuration based on a first base current through a first base of the first pnp transistor and a second base current through a second base of the second pnp transistor, the one or more pnp transistors comprising the first and second pnp transistors. Calibration circuit 208 may further generate an initial proportional-to-temperature voltage (an “initial PTAT voltage”) at a first node of a voltage divider (e.g., n1), connected at the first base of the first pup transistor, based on removing a current equal to the first base current (e.g., IbaseQ1) from the voltage divider. The removed current may be based on, for example, a difference between a first voltage potential (e.g., Vn1) at the first base of the first pnp transistor and a second voltage potential (e.g., Vn4) based on a resistor connected to a second base of the second pnp transistor. The calibrated PTAT voltage may be based on a function of the initial PTAT voltage. The first calibrated voltage may be generated based on a sum of the base-emitter voltage of one of the pnp transistors and the calibrated PTAT voltage.

ADC 202 generates a set of reference values based at least our the first calibrated voltage, the second calibrated voltage, and the stress-impaired reference voltage (604). A first reference value of the set of reference values may be determined based on the first calibrated voltage and the stress-impaired reference voltage, and a second reference value of the set of reference values may be determined based on the second calibrated voltage and the stress-impaired reference voltage. A third reference value of the set of reference values may be determined based on the calibrated PTAT voltage and the stress-impaired reference voltage.

Processing unit 210 calculates a gain correction factor based on a function of the set of reference values and a set of temperature-dependent values (606). In some implementations, a temperature is calculated based on an initial gain correction value and a first reference value of the set of reference values. The set of temperature-dependent values may be calculated based on the calculated temperature. In some implementations, determining the set of temperature-dependent values may be based on indexing a lookup table by the calculated temperature. When calculating the gain correction factor, processing unit 210 may repeat the calculation of the temperature, the set of temperature-dependent values, and the gain correction factor until the temperature and the gain correction factor converge to respective values. In this regard, each temperature calculation may be based on a last-calculated gain correction factor.

In some implementations, calculating the gain correction factor may include multiplying each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum. In some implementations, calculating the gain correction factor may include generating one or more polynomial equations based on the set of reference values the set of temperature-dependent values, the first calibrated voltage, the second calibrated voltage, the calibrated PTAT voltage, and the stress-impaired reference voltage, and solving for unknown values within the polynomial equations. For example, two polynomial equations may be solved for unknown gain correction factor G and a change in stress Δσ.

Processing unit 210 receives an output signal based on the stress-impaired reference voltage (608), and adjusts (e.g., corrects) the output signal based on the gain correction factor (610). As described previously, since device temperature T by way of the foregoing calculations is a corrected value, the various systems of the present disclosure may function as a stress-compensated integrated temperature sensor by providing T as an output value.

The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

Accordingly, implementations and practices according to the disclosed aspects can include a non-transitory computer readable media embodying a method for de-duplication of a cache. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.

While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated. 

What is claimed is:
 1. A method, comprising: receiving a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a stress-impaired reference voltage; determining a set of reference values based on the first calibrated voltage, the second calibrated voltage, and the stress-impaired reference voltage; calculating a gain correction factor based on a function of the set of reference values and a set of temperature-dependent values; receiving an output signal based on the stress-impaired reference voltage; and adjusting the output signal based on the gain correction factor.
 2. The method of claim 1, further comprising: calculating a temperature based on an initial gain correction value and a first reference value of the set of reference values; calculating the set of temperature-dependent values based on the calculated temperature; and repeating the calculation of the temperature, the set of temperature-dependent values, and the gain correction factor until the temperature and the gain correction factor converge to respective values, wherein each temperature calculation is based on a last-calculated gain correction factor.
 3. The method of claim 2, further comprising: determining the set of temperature-dependent values based on indexing a lookup table by the calculated temperature; wherein calculating the gain correction factor comprises multiplying each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum.
 4. The method of claim 1, further comprising: receiving a first voltage that is proportional to absolute temperature (a calibrated PTAT voltage) based on a base-emitter voltage of one of the pnp transistors, wherein a first reference value of the set of reference values is determined based on the first calibrated voltage and the stress-impaired reference voltage, wherein a second reference value of the set of reference values is determined based on the second calibrated voltage and the stress-impaired reference voltage, wherein a third reference value of the set of reference values is determined based on the calibrated PTAT voltage and the stress-impaired reference voltage.
 5. The method of claim 4, wherein calculating the gain correction factor comprises: determining the gain correction factor from one or more polynomial equations based on the set of reference values the set of temperature-dependent values, the first calibrated voltage, the second calibrated voltage, the calibrated PTAT voltage, and the stress-impaired reference voltage.
 6. The method of claim 4, wherein the first calibrated voltage corresponds to a sum of the base-emitter voltage of the one or more pnp transistors and the calibrated PTAT voltage.
 7. The method of claim 6, wherein the first calibrated voltage, the second calibrated voltage, and the calibrated PTAT voltage are generated by a reference circuit, the reference circuit configured to: operate first and second pnp transistors in a matched pair configuration based on a first base current through a first base of the first pnp transistor and a second base current through a second base of the second pnp transistor, the one or more pnp transistors comprising the first and second pnp transistors; and generate an initial proportional-to-temperature voltage (an initial PTAT voltage) at a first node of a voltage divider, connected at the first base of the first pnp transistor, based on removing a current based on the first base current from the voltage divider, wherein the calibrated PTAT voltage is based on a function of the initial PTAT voltage.
 8. The method of claim 7, wherein the removed current is based on a difference between a first voltage potential at the first base of the first pap transistor and a second voltage potential based on a resistor connected to a second base of the second pnp transistor.
 9. The method of claim 7, wherein a multiplexer provides, to an analog-to-digital converter, an analog signal selected from the first calibrated voltage, the second calibrated voltage, the calibrated PTAT voltage, and one or more analog input signals, wherein the analog-to-digital converter generates each respective reference value of the set of reference values based on the stress-impaired reference voltage and a selected one of the first calibrated voltage, the second calibrated voltage, and the calibrated PTAT voltage, and generates the output signal based on the stress-impaired reference voltage and the analog input signal, and wherein a processor receives the set of reference values and the output signal from the analog-to-digital converter, calculates the gain correction factor, and adjusts the output signal based on the gain correction factor.
 10. A circuit, comprising: means for receiving a first calibrated voltage based on a base-emitter voltage of one or more pnp transistors, a second calibrated voltage based on a base-emitter voltage of one or more npn transistors, and a stress-impaired reference voltage; means for determining a set of reference values based on the first calibrated voltage, the second calibrated voltage, and the stress-impaired reference voltage; means for calculating a gain correction factor based on a function of the set of reference values and a set of temperature-dependent values; means for receiving an output signal based on the stress-impaired reference voltage; and means for correcting the output signal based on the gain correction factor.
 11. A system for calibrating a stress-impaired output signal, comprising: a calibration circuit providing a first calibrated pnp voltage based on a base-emitter voltage of one or more pnp transistors and a second calibrated npn voltage based on a base-emitter voltage of one or more npn transistors; a multiplexer connected to the calibration circuit and a sense terminal, and configured to provide an analog signal selected from a sense signal at the sense terminal, the first calibrated pnp voltage, and the second calibrated npn voltage; and an analog-to-digital converter configured to generate a digital output signal based on the analog signal selected by the multiplexer and a stress-impaired reference voltage; a processor, the processor configured to: control the multiplexer to sample the first calibrated pnp voltage, the second calibrated npn voltage, and the sense signal for the analog-to-digital converter; receive a set of reference values from the analog-to-digital converter based on the stress-impaired reference voltage and a sampling of the first calibrated pnp voltage and the second calibrated npn voltage by the multiplexer; calculate a gain correction factor based on a set of reference values and a set of temperature-dependent values; adjust the digital output signal based on the gain correction factor to correct for errors introduced by the stress-impaired reference voltage.
 12. The system of claim 11, wherein the processor is further configured to: calculate a temperature based on an initial gain correction value and a first reference value of the set of reference values; calculate the set of temperature-dependent values based on the calculated temperature; and repeat calculations of the temperature, the set of temperature-dependent values, and the gain correction factor until the temperature and the gain correction factor converge to respective values, wherein each temperature calculation is based on a last-calculated gain correction factor.
 13. The system of claim 12, wherein the processor is further configured to: determine the set of temperature-dependent values based on indexing a lookup table by the calculated temperature; wherein calculating the gain correction factor comprises multiplying each temperature-dependent value in the set of temperature-dependent values by a respective reference value of the set of reference values, summing each result, and determining a reciprocal of the sum.
 14. The system of claim 12, wherein the processor is further configured to: provide an output temperature value based on a convergence of the repeated calculations of the temperature.
 15. The system of claim 11, wherein the calibration circuit further provides a voltage that is proportional to absolute temperature (a calibrated PTAT voltage) based on the base-emitter voltage of one of the pnp transistors, wherein a first reference value of the set of reference values is determined based on the first calibrated pnp voltage and the stress-impaired reference voltage, wherein a second reference value of the set of reference values is determined based on the second calibrated npn voltage and the stress-impaired reference voltage, and wherein a third reference value of the set of reference values is determined based on the calibrated PTAT voltage and the stress-impaired reference voltage.
 16. The system of claim 15, wherein the gain correction factor is determined from one or more polynomial equations based on the set of reference values the set of temperature-dependent values, the first calibrated pnp voltage, the second calibrated npn voltage, the calibrated PTAT voltage, and the stress-impaired reference voltage.
 17. The system of claim 16, wherein the first calibrated pnp voltage corresponds to a sum of the base-emitter voltage of the one or more pnp transistors and the calibrated PTAT voltage.
 18. The system of claim 17, wherein the calibration circuit is configured to: operate first and second pnp transistors in a matched pair configuration based on a first base current through a first base of the first pnp transistor and a second base current through a second base of the second pnp transistor, the one or more pnp transistors comprising the first and second pnp transistors; and generate an initial proportional-to-temperature voltage (an initial PTAT voltage) at a first node of a voltage divider, connected at the first base of the first pnp transistor, based on removing a current based on the first base current from the voltage divider, wherein the calibrated PTAT voltage is based on a function of the initial PTAT voltage.
 19. The system of claim 18, wherein the removed current is based on a difference between a first voltage potential at the first base of the first pnp transistor and a second voltage potential based on a resistor connected to a second base of the second pnp transistor.
 20. The system of claim 18, wherein the multiplexer provides an analog signal selected from a sense signal at the sense terminal, the first calibrated pnp voltage, the second calibrated npn voltage, and the calibrated PTAT voltage, wherein the analog-to-digital converter generates each respective reference value of the set of reference values based on the stress-impaired reference voltage and a selected one of the first calibrated pnp voltage, the second calibrated npn voltage, and the calibrated PTAT voltage. 